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-- Company: 
-- Engineer:
--
-- Create Date:   03:03:24 10/06/2009
-- Design Name:   
-- Module Name:   /usa/mcgraw/CPEG422/proj1/program_tb.vhd
-- Project Name:  proj1
-- Target Device:  
-- Tool versions:  
-- Description:   
-- 
-- VHDL Test Bench Created by ISE for module: program
-- 
-- Dependencies:
-- 
-- Revision:
-- Revision 0.01 - File Created
-- Additional Comments:
--
-- Notes: 
-- This testbench has been automatically generated using types std_logic and
-- std_logic_vector for the ports of the unit under test.  Xilinx recommends
-- that these types always be used for the top-level I/O of a design in order
-- to guarantee that the testbench will bind correctly to the post-implementation 
-- simulation model.
--------------------------------------------------------------------------------
LIBRARY ieee;
USE ieee.std_logic_1164.ALL;
USE ieee.std_logic_unsigned.all;
USE ieee.numeric_std.ALL;
 
ENTITY program_tb IS
END program_tb;
 
ARCHITECTURE behavior OF program_tb IS 
 
    -- Component Declaration for the Unit Under Test (UUT)
 
    COMPONENT program
    PORT(
         clk : IN  std_logic;
         reset : IN  std_logic;
         keyboard_ascii : IN  std_logic_vector(7 downto 0);
         keyboard_ready : IN  std_logic;
         ascii_code : OUT  std_logic_vector(7 downto 0);
         lcd_data_ready : OUT  std_logic;
         leds : OUT  std_logic_vector(7 downto 0)
        );
    END COMPONENT;
    

   --Inputs
   signal clk : std_logic := '0';
   signal reset : std_logic := '0';
   signal keyboard_ascii : std_logic_vector(7 downto 0) := (others => '0');
   signal keyboard_ready : std_logic := '0';

 	--Outputs
   signal ascii_code : std_logic_vector(7 downto 0);
   signal lcd_data_ready : std_logic;
   signal leds : std_logic_vector(7 downto 0);

   -- Clock period definitions
   constant clk_period : time := 1us;
 
BEGIN
 
	-- Instantiate the Unit Under Test (UUT)
   uut: program PORT MAP (
          clk => clk,
          reset => reset,
          keyboard_ascii => keyboard_ascii,
          keyboard_ready => keyboard_ready,
          ascii_code => ascii_code,
          lcd_data_ready => lcd_data_ready,
          leds => leds
        );

   -- Clock process definitions
   clk_process :process
   begin
		clk <= '0';
		wait for clk_period/2;
		clk <= '1';
		wait for clk_period/2;
   end process;
 

   -- Stimulus process
   stim_proc: process
   begin		
      -- hold reset state for 100ms.
      wait for 100ms;	

      wait for clk_period*10;

      -- insert stimulus here 

      wait;
   end process;

END;
